1. Field of the Invention
The present invention relates generally to methods for forming vias through silicon containing dielectric layers within microelectronics fabrications. More particularly, the present invention relates to plasma etch methods for forming residue free vias through silicon containing dielectric layers when accessing metal layers within microelectronics fabrications.
2. Background of the Invention
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned conductor layers which are separated by dielectric layers. Patterned conductor layers within microelectronics fabrications are typically, although not exclusively, formed of conductor materials such as but not limited to metals, metal alloys, doped polysilicon and polycides (doped polysilicon/metal silicide stacks). Similarly, dielectric layers which separate patterned conductor layers within microelectronics fabrications are typically, although not exclusively, formed of silicon containing dielectric materials such as but not limited to silicon oxide dielectric materials, silicon nitride dielectric materials, silicon oxynitride dielectric materials and composites of silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials.
In the process of forming microelectronics fabrications from microelectronics substrates, it is common in the art of microelectronics fabrication to: (1) connect patterned conductor layers with microelectronic devices within those microelectronics fabrications through contact vias formed through silicon containing dielectric layers within those microelectronics fabrications; and (2) interconnect patterned conductor layers with other patterned conductor layers within those microelectronics fabrications through interconnection vias also formed through silicon containing dielectric layers within those microelectronics fabrications.
Thus, while contact vias and interconnection vias are commonly and desirably formed through silicon containing dielectric layers within microelectronics fabrications, contact vias and interconnection vias are typically not formed entirely without problems through silicon containing dielectric layers within microelectronics fabrications. In particular, it is known in the art of microelectronics fabrication that contact vias or interconnection vias when formed through plasma etch methods through silicon containing dielectric layers within microelectronics fabrications to access patterned conductor metal contact layers or patterned conductor metal interconnection layers within microelectronics fabrications often have metal-fluoropolymer residue layers formed upon the patterned conductor metal contact layers or patterned conductor metal interconnection layers accessed by the contact vias or the interconnection vias. The metal-fluoropolymer residue layers formed upon the patterned conductor metal contact layers or the patterned conductor metal interconnection layers within the contact vias or the interconnection vias typically derive at least in part from: (1) etchant gas compositions employing fluorine containing etchant gases which are employed when plasma etching vias through silicon containing dielectric layers; along with (2) metal from the patterned conductor metal contact layers or the patterned conductor metal interconnection layers which are accessed and etched within the plasma etch methods when forming and over-etching those contact vias and interconnection vias through the silicon containing dielectric layers.
Metal-fluoropolymer residue layers are undesirable when formed upon patterned conductor metal contact layers or patterned conductor metal interconnection layers within contact vias or interconnection vias through silicon containing dielectric layers within microelectronics fabrications since it is typically difficult to subsequently form within contact vias or interconnection vias having metal-fluoropolymer residues layers formed therein conductor contact stud layers or conductor interconnection stud layers with desirably low and reproducible contact resistances. It is thus towards the goal of forming within microelectronics fabrications, through plasma etch methods, contact vias and interconnection vias through silicon containing dielectric layers to access patterned conductor metal contact layers and patterned conductor metal interconnection layers without forming metal-fluoropolymer residue layers upon patterned conductor metal contact layers and the patterned conductor metal interconnection layers accessed through those contact vias and interconnection vias that the present invention is more specifically directed.
Various novel plasma etch methods have been disclosed in the art of microelectronics fabrication for forming patterned layers within microelectronics fabrications.
For example, Hwang et al., in U.S. Pat. No. 5,174,856, discloses a plasma etch stripping method for removing from a chlorine containing plasma etched patterned metal layer within an integrated circuit microelectronics fabrication a photoresist etch mask layer employed in defining the chlorine containing plasma etched patterned metal layer. The plasma stripping method employs an oxygen containing stripping gas composition followed by an oxygen and ammonia containing stripping gas composition to strip from the chlorine containing plasma etched patterned metal layer the patterned photoresist etch mask layer while providing the chlorine containing plasma etched patterned metal layer which is inhibited from chlorine containing plasma residue corrosion for a minimum of 24 hours.
In addition, Lai, in U.S. Pat. No. 5,188,980, discloses a plasma etch method for forming within an integrated circuit microelectronics fabrication a polycide gate structure while avoiding undercutting of a metal silicide layer within the polycide gate structure. The method employs a first chlorine and helium etchant gas composition when plasma etching the metal silicide layer within the polycide gate structure followed by a helium purge prior to employing a second chlorine and helium etchant gas composition when plasma etching a polysilicon layer within the polycide gate structure.
Finally, Liu, in U.S. Pat. No. 5,609,775, discloses a plasma etch method for forming a composite aluminum upper layer/titanium-tungsten middle layer/titanium lower layer patterned layer within an integrated circuit microelectronics fabrication with: (1) improved etch selectivity of the titanium-tungsten middle layer with respect to a patterned photoresist etch mask layer employed in defining the composite aluminum upper layer/titanium-tungsten middle layer/titanium lower layer patterned layer; and (2) attenuated sidewall taper of the composite aluminum upper layer/titanium-tungsten middle layer/titanium lower layer patterned layer. To provide the improved etch selectivity, the plasma etch method employs a carbon tetrafluoride etchant gas within the etchant gas composition employed in etching the titanium-tungsten middle layer. To provide the attenuated sidewall taper, the plasma etch method employs a nitrogen etching gas within the etchant gas compositions employed in etching each of the layers within the composite aluminum upper layer/titanium-tungsten middle layer/titanium lower layer patterned layer.
Desirable in the art of microelectronics fabrication are plasma etch methods through which may be formed vias through silicon containing dielectric layers to access conductor metal layers without forming metal-fluoropolymer residue layers upon the conductor metal layers accessed through the vias. It is towards those objects that the present invention is generally directed.